1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and in particular, a nonvolatile semiconductor memory device arranged with a plurality of nonvolatile semiconductor memory devices.
2. Description of the Related Art
There is a tendency to adopt methods for increasing the number of memory cells which are read once with the aim of improving the capabilities in addition to large capacity in a NAND type flash memory. Consequently, improvements in drive ability of a cell source line into which a large current flows or a ground driver of a cell well line for suppressing noise are being desired. In answer to such demands, methods are being proposed such as the method disclosed in the nonvolatile semiconductor memory device in the Japanese Laid Open Patent 2006-302960, for example, in which the ground capability of a ground driver is maximized by arranging a high voltage transistor region between a sense amplifier region and a memory cell array.
In addition, in the Japanese Laid Open Patent 2006-302960, a cell source line, cell well line and power supply line are connected to the source/drain of a high voltage transistor which comprises a ground driver. However, in an actual chip, the wiring layer immediately above a ground driver are covered by a wire which connects a bit line and a sense amplifier region, the wire pitch becomes more narrow with the progress of high integration and it becomes more difficult to pass the wires themselves through. Consequently, even if the width of a wire becomes smaller due to miniaturization, it becomes more difficult to pass a cell source line, cell well line and power supply line through a wiring layer.
Also, in the nonvolatile semiconductor memory device in Japanese Laid Open Patent 2006-245547, a method is proposed for maximizing the grounding ability of a ground driver by lowering the resistance of a cell source line, cell well line and power supply line which are arranged above a cell array. Furthermore, there is a tendency for a consumption current to increase with large capacity memory and high functionality and while further strengthening of a power supply line is becoming essential, in order to achieve this an increase in the width of power supply line is required which leads to an increase in the size of a chip.